CS 351 Computer Architecture

Fall 2009, Sonoma State University

Instructor:

B. Ravikumar. Office: 116 I, Darwin Hall

Office phone: 664 3335 Email: ravi@cs.sonoma.edu.

Office hours: TBA

 

Class Time and place: M W 10 to 11:50 PM. 31, Darwin Hall

 

Catalog Description:

 Lecture, 4 hours. Instruction set design; stages of instruction execution, data and control path design; CISC, RISC, stack architectures; pipelining; program optimization techniques, memory hierarchy: cache models and design issues, virtual memory and secondary storage; I/O interfacing; advanced topics to include some of the following: parallel architectures, DSP or other special purpose architecture, FPGA, reconfigurable architecture, asynchronous circuit design.
Prerequisite: CS 215 and 252, or consent of instructor.
 

 

Course Goals:

 Computer architecture deals with the functionality of all the major components of a computer: ALU, control and data paths, cache and main memory, I/O, interconnections etc. The programmer's view of the instruction set and user interface will be considered along with memory organization, addressing methods, implementation of control, and a multitude of performance issues and trade-offs. The main focus will be on the following topics: performance measures of computer systems, MIPS assembly language, computer arithmetic and ALU circuit design, CPU design, pipelining, cache memory, multicore CPU and parallel programming.

 

Text:

Computer Organization and Design, Fourth Edition, Fourth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design)Computer Organization and Design: The hardware/software interface, 4th edition, Morgan-Kaufman Publishers, ISBN: 978-0-123744937.  

 

 

Topics Covered in detail:

 

The following is a tentative list of topics:

  • Review of digital design and overview of the course: history of computer designs, circuit models and design, new developments, performance issues (Ch 1)
  • Instruction set and MIPS assembly language: instruction types, encoding, RISC model, MIPS assembly language and instruction set design. (Ch 2)
  • Computer arithmetic and ALU design: number systems, floating-point encoding, adder, multiplier, division, FP processor design. (Ch 3)
  • Data and Control Path Design: (Ch 4)
  • Cache Memory: (Ch 5)
  • Advanced Topics: Multiprocessors and parallel programming (Ch 7), GPGPU (Appendix A)

 

Other References:

  • Parhami, Behrooz, Computer Architecture: From Microprocessors to Supercomputers, Oxford University Press, 556 + xx pp., February 2005 (ISBN 0-19-515455-X).
  • M. Murdocca and V. Heuring, Computer Architecture, Prentice-Hall.
  • W. Stallings, Computer Organization and Architecture: Designing for Performance, Prentice-Hall.

  

Assigned Work and Evaluation:

         Quiz (10 - 15%) There will be a quiz every class. Duration: 10 to 15 minutes.

         Two Mid-Term tests (20 - 25%) Both tests will be in class and will be about 100 minutes long. Each test will have a closed-book and an open-book section.

         Home Work assignments (20 - 25%) This will include some implementation (in MIPS assembly language, hardware description language etc.) as well as other design and problem solving exercises.

         Final Examination (35 - 40%) The final examination will be comprehensive and will have a closed- and an open-book section.

 

Online sources:

http://www.cs.wisc.edu/arch/www/ is a repository of information on all aspects of computer architecture: education, research, industrial practice etc. Various simulation tools can also be accessed from here.

 

http://webcast.berkeley.edu/course_details.php?seriesid=1906978259 contains video-taped lectures by Patterson, one of the authors of the text.